Problems with icepll

Topics FPGA
1

I noticed something strange with icepll:

% icepll -i 12 -o 100

F_PLLIN:    12.000 MHz (given)
F_PLLOUT:  100.000 MHz (requested)
F_PLLOUT:  100.500 MHz (achieved)

FEEDBACK: SIMPLE
F_PFD:   12.000 MHz
F_VCO:  804.000 MHz

DIVR:  0 (4'b0000)
DIVF: 66 (7'b1000010)
DIVQ:  3 (3'b011)

FILTER_RANGE: 1 (3'b001)

Why can’t it create exactly 100 MHz?
I would use

DIVR:  2
DIVF: 49
DIVQ: 1

According to the formula on page 7 (‘iCE40sysCLOCKPLLDesignandUsageGuide’) this gives 100 MHz and the VCO runs at 600MHz. Anything wrong with that?

2

PFD frequency with DIVR=2 would be outside of the supported range (10 - 133 MHz)

3

bummer! Thank you for your help