Migrating PLL from HX1K to HX4K

Topics FPGA
1

I previously made a PLL for a 201MHz clock on my HX1K FPGA, but now I want to migrate my code to the larger HX4K FPGA, but the PLL isn’t working on the new chip. They are both the TQ-144 type chip. My code passes iceStorm’s verification and build stages as successes, but when tying pll_clk to an output pin to view it on a scope, but now signal appears.

         input  clk //pin 21
    );
	
	wire pll_clk;
	// PLL (201 MHz)
    SB_PLL40_CORE #(
        .FEEDBACK_PATH("SIMPLE"),   // Don't use fine delay adjust
        .PLLOUT_SELECT("GENCLK"),   // No phase shift on output
        .DIVR(4'b0000),             // Reference clock divider
        .DIVF(7'b1000010),          // Feedback clock divider
        .DIVQ(3'b010),              // VCO clock divider
        .FILTER_RANGE(3'b001)       // Filter range
    ) pll (
        .REFERENCECLK(clk),     // Input clock
        .PLLOUTCORE(pll_clk),           // Output clock
        .LOCK(),                    // Locked signal
        .RESETB(1'b1),              // Active low reset
        .BYPASS(1'b0)               // No bypass, use PLL signal as output
    );