I have this idea in mind and was hoping people here could pick holes in it or flag any risks, considering I can’t run my designs on a board yet and even if it does work, I want to be certain it’s reliable:
- 12mhz in to SB_PLL40_2F_PAD
- 25mhz out to GLOBALA
- 12.5mhz out to GLOBALB using GENCLK_HALF
The 2F_PAD seems to support this from looking at existing designs.
Can I assume that the 25mhz and 12.5mhz are in phase or close enough to it, such that the posedge of the half-speed clock aligns with the posedge of every other full-speed clock? Or do I need to do the whole CDC thing in this case? Any input appreciated