Here you can discuss all things Field Programmable Gate Array (FPGA) related topics. Feel free to show off your digital design projects (IP) and ask questions about FPGA tools.
Our community is mostly interested in open-source, so this is not the right place to ask questions about closed source FPGA tools. The vendors of proprietary tools have forums for that, we might try to answer your questions but the answer will likely be “No idea. Are you sure you can’t use an FPGA that is supported by the open tools instead?”. But if you have any questions related to the open-source FPGA flow this is one of the good places to ask your questions. This is also the right place to ask about HDL design. If you are asking a question related to #projects:nmigen we have a dedicated category for that project. 
Here are some useful keywords and links:
- yosys (Yosys Open SYnthesis Suite
- nextpnr (Place and Router)
- icestorm (Lattice iCE40 technology database and tools)
- prjtrellis (Lattice ECP5 technology database)
- … (let us know what should be added here)